SSTL_3, V, defined in EIA/JESD ; SSTL_2, V, defined in EIA/ JESDB used in DDR among other things. SSTL_18, V, defined in. STUB SERIES TERMINATED. LOGIC FOR VOLTS (SSTL_2). EIA/JESD SEPTEMBER ELECTRONIC INDUSTRIES ALLIANCE. JEDEC Solid State . SSTL (JESD, JESDB, JESD). • HSTL (JESD). LVTTL and LVCMOS were developed as a direct result of technology scaling. With each reduction in.
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The standard defines a reference voltage VREF which is used at the receivers as well as a voltage VTT to which termination resistors are connected. However, in the case of VIH Max. Jwsd8 claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.
However a Class II buffer would dissipate more power due to its larger current drive and thus might require special cooling. Note however, that all timing specifications are still set relative to the ac input level. With a series resistor of 25?
Stub Series Terminated Logic
In this example a Class II type buffer might be preferred since it comes closer, in conjunction with the series resistor, to match the characteristic impedance of the transmission line. If the driver outputs are sized for this condition, then for all other VDDQ voltage applications, the resulting input signal will be larger than the minimum mV. One advantage of this approach is that there is no need for a VTT power supply. See also figure 2. NOTE 4 AC test conditions may be measured under nominal voltage conditions as long as the supplier can demonstrate by analysis that the device will meet its timing specifications under all supported voltage conditions.
Typically the value of VREF is expected to be 0. The relationship of the different levels is shown in figure 1. The specifications are quite different from traditional specifications, where minimum values for VOH and maximum values for VOL are set that apply to the entire supply range.
JEDEC is the leading developer of standards for the solid-state industry, they have published over documents to date. If you have downloaded the file prior to date of errata please reprint page 7.
F or info rm jese8con tact: Under these conditions VOH is 1. The ac values are chosen to indicate the levels at which jssd8 receiver must meet its timing specifications. By downloading this file the individual agrees not to charge for or resell the resulting material.
The output specifications are divided into two classes, Class I and Class II, which are distinguished by drive requirements and application. The second clause defines the minimum dc and ac input parametric requirements and ac test conditions for inputs on compliant devices. This clause is 99b to set the conditions under which the driver ac specifications can be tested.
However, the drivers are connected directly onto the bus so there are no stubs present. Class I jezd8 Units V V Notes 2.
An example of this is shown in figure 6. Figure 3 shows the typical dc environment that the output buffer is presented with. In this non binding section we will show some derived applications. In some standards this ratio equals 0. Units V mV Notes 1 1 0.
EIA JEDEC STANDARD jesdb-sstl_2_百度文库
In that case, the designer may decide to eliminate the series resistors entirely. Vx ac indicates the voltage at which differential input signals must be crossing. NOTE 2 A 1. The tester may therefore supply signals with a 1. Busses may be terminated by resistors to an external termination voltage. The system designer can be sure that the device will switch state a certain amount of time after the input has crossed ac threshold and not switch back as long as the input stays beyond the dc threshold.
JEDEC standards and publications are designed to 9h the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. While driver characteristics jeesd8 derived from a 50?
The dc values are chosen such that the final logic state is unambiguously defined, that is once the receiver input has crossed this value, the receiver will change to and maintain the new logic state.
This is accomplished precisely because drivers and receivers are specified independently of each other. O rgan iz atio ns m ay ob tain perm issio n to rep rod uce a lim ited n um b er o f co pies thro ugh enterin g in to a licen se agreem en t. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments.
Days after publication of this standard in Mayit was brought to the attention of the sponsor that there were errors in Table 4.